The present invention relates to a method and a device for erasing a non-volatile semiconductor memory. The erasing method and device of the present invention is particularly suitable for a semiconductor memory such as a flash EEPROM that carries out write-in operation by using hot electron injection and is erased by FN (Fowler-Nordheim) tunneling.
Electrically erasable and programmable read-only memories (EEPROMs) are well known as an example of the non-volatile semiconductor memory. In the non-volatile semiconductor memories of the type described, a plurality of memory cells form a memory cell array. Each memory cell has a floating gate that is electrically insulated between a control gate of an MOS transistor and a silicon substrate.
Electrons trapped in the floating gates in the non-volatile semiconductor memory can be discharged by applying a zero voltage or a negative voltage and a positive voltage (e.g., +12 V) for electron discharge to the control gate and a source, respectively, with a drain of the memory cell being in a floating state. A high electrical field is generated from the source of the memory cell toward the floating gate, providing an FN (Fowler-Nordheim) current from the source of the memory cell to the floating gate. As is well known in the art, electrons travel in the opposite direction to electrical current does. Thus the electrons are discharged from the floating gate. The positive voltage is generally supplied through a source voltage control circuit for the electron discharge applied to the source of the memory cell for the electron discharge operation.
Examples of memory erase operation for such non-volatile semiconductor memories are disclosed in, for example, U.S. Pat. No. 5,077,691 (hereinafter, referred to as a first conventional example) and U.S. Pat. No. 5,485,423 (hereinafter, referred to as a second conventional example). Briefly, the first conventional example opens a drain (column line) of a memory cell during erase operation. A positive voltage (e.g., +5 V) and a negative voltage (e.g., -12 V) are applied to a source and a gate, respectively, of the memory cell to erase data. The second conventional example opens a drain of a memory cell during erase operation. A constant positive voltage (e.g., +5 V) is applied to a source of the memory cell. Simultaneously, a negative step-shaped voltage that is gradually decreased is applied to a gate of the memory cell.
If the drain in the first conventional example is opened with the column line carrying the voltage, a ratio of capacity (across the gate and the source) varies partially (line by line) increasing erase variation upon the erase operation due to the residual voltage. In addition, the timing to apply the voltage across the gate and the source may change operation mode into a channel erase mode.
The second conventional example has the effect of reducing the electrical field across a tunnel film. However, this second conventional example has the following drawbacks. The negative step-shaped voltage that is gradually decreased is controlled according to a time during which it is applied to, without detecting the voltage actually applied across the gate. The effect of the reduction of the electrical field thus depends on an erase rate, which is not considered to be sufficient. In addition, the problem of the erase variation is not solved as in the first conventional example.